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? 2005 fairchild semiconductor corporation ds500172 www.fairchildsemi.com august 1998 revised january 2005 gtlp16t1655 16-bit lvttl/gtlp universal bus transceiver with high drive gtlp and individual byte controls gtlp16t1655 16-bit lvttl/gtlp universal bus transceiver with high drive gtlp and individual byte controls general description the gtlp16t1655 is a 16-bit universal bus transceiver that provides lvttl to gtlp signal level translation. it allows for transparent, latched and clocked modes of data transfer. the device provides a high speed interface between cards operating at lvttl logic levels and a back- plane operating at gtlp logic levels. high speed back- plane operation is a direct result of gtlp?s reduced output swing ( < 1v), reduced input threshold levels and output edge rate control. the edge rate control minimizes bus set- tling time. gtlp is a fairchild semiconductor derivative of the gunning transceiver logic (gtl) jedec standard jesd8-3. fairchild?s gtlp has internal edge-rate control and is pro- cess, voltage, and temperature (pvt) compensated. its function is similar to btl and gtl but with different output levels and receiver threshold. gtlp output low level is typically less than 0.5v, the output level high is 1.5v and the receiver threshold is 1.0v. features bidirectional interface between gtlp and lvttl logic levels variable edge rate control pin to select desired edge rate on the gtlp backplane (v erc ) v ref pin provides external supply reference voltage for receiver threshold adjustibility special pvt compensation circuitry to provide consis- tent performance over variations of process, supply volt- age and temperature ttl compatible driver and control inputs designed using fairchild advanced bicmos technology bushold data inputs on a port to eliminate the need for external pull-up resistors for unused inputs power up/down and power off high impedance for live insertion open drain on gtlp to support wired-or connection flow through pinout optimizes pcb layout d-type flip-flop, latch and transparent data paths a port source/sink ? 24ma/ + 24ma b port sink + 100ma partitioned as two 8-bit transceivers with individual latch timing and output control but with a common clock external pin to pre-condition i/o capacitance to high state (v ccbias ) ordering code: devices also available in tape and reel. specify by appending the suffix letter ? x ? to the ordering code. order number package number package description gtlp16t1655mtd mtd64 64-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide
www.fairchildsemi.com 2 gtlp16t1655 connection diagram pin descriptions truth tables (note 1) note 1: a-to-b data flow is shown. b-to-a data flow is similar but uses oeba , leba, clk. note 2: output level before the indicated steady state input conditions were established, provided clk was high prior to leab going low . note 3: output level before the indicated steady state input conditions were established. note 4: oeab and oeba are byte-wide enables. each is proceeded by a number indicating the byte controlled. pin names description 1oeab a-to-b output enable (active low) 2oeab byte 1 and byte 2 1oeba b-to-a output enable (active low) 2oeba byte 1 and byte 2 oe disables all i/o ports simultaneously 1leab a-to-b latch enable (transparent high) 2leab byte 1 and byte 2 1leba b-to-a latch enable (transparent high) 2leba byte 1 and byte 2 v ref gtlp reference voltage clk a-to-b and b-to-a clock 1a1-1a8 a port i/o byte 1 and byte 2 2a1-2a8 1b1-1b8 b port i/o byte 1 and byte 2 2b1-2b8 inputs output mode oeab leab clk a b h x x x z high impedance l h x l l transparent l h x h h transparent ll l l registered ll h h registered llhxb 0 (note 2) previous state lllxb 0 (note 3) previous state inputs outputs inputs output edge oe oeab (note 4) oeba (note 4) a port b port v erc b port l l l active active v cc slow l l h z active gnd fast l h lactivez lhhzz hxxzz
3 www.fairchildsemi.com gtlp16t1655 functional description the gtlp16t1655 is a high drive (100 ma) 16-bit univer- sal bus transceiver containing d-type flip-flop, latch and transparent modes of operation for the data path. the device is uniquely partitioned as two 8-bit transceivers with individual latch timing and output control signals but with a common clock pin (clk) for both transceiver words. data flow for each word is determined by the respective latch enables (xleab and xleba), output enables (xoeab and xoeba ) and clock (clk). the output enables (1oeab , 1oeba , and 2oeab and 2oeba ) control byte1 and byte2 data for the a to b and b to a directions respectively. for a-to-b data flow, the devices operate in the transparent mode when leab is high. when leab transitions low, the a data is latched independent of clk high or low. if leab is low the a data is registered on the clk low-to-high transition. when oeab is low the outputs are active. with oeab high the outputs are high imped- ance. data flow for the b-to-a direction is identical but uses oeba , leba and clk. note that clk is common to both directions and both 8-bit words. oe is also common and is used to disable all i/o ports simultaneously. logic diagrams
www.fairchildsemi.com 4 gtlp16t1655 absolute maximum ratings (note 5) recommended operating conditions note 5: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rating. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 6: i o absolute maximum rating must be observed. note 7: v tt and r term can be adjusted to accommodate backplane imped- ances other than 50 ? , within the boundaries of not exceeding the dc absolute i ol ratings (200 ma). similarly v ref can be adjusted to compen- sate for changes in v tt . dc electrical characteristics over recommended operating free-air temperature range, v ref = 1.0v (unless otherwise noted). supply voltage (v cc ) ? 0.5v to + 4.6v dc input voltage (v i ) ? 0.5v to + 4.6v dc output voltage (v o ) outputs 3-state ? 0.5v to + 4.6v outputs active (note 6) ? 0.5v to + 4.6v dc output sink current into a port i ol 48 ma dc output source current from a port i oh ? 48 ma dc output sink current into b port in the low state, 200 ma i ol (note 7) dc input diode current (i ik ) v i < 0v ? 50 ma dc output diode current (i ok ) v o < 0v ? 50 ma v o > v cc + 50 ma esd rating > 2000v storage temperature (t stg ) ? 65 c to + 150 c supply voltage v cc 3.0v to 3.6v bus termination voltage (v tt ) gtlp 1.35v to 1.65v gtl 1.14v to 1.26v v ref gtlp 0.87v to 1.1v gtl 0.74v to 0.87v input voltage (v i ) on a port and control pins 0.0v to v cc on b port 0.0v to v tt high level output current (i oh ) a port ? 24 ma low level output current (i ol ) a port + 24ma b port + 100 ma operating temperature (t a ) ? 40 c to + 85 c symbol test conditions min typ max units (note 8) v ih b port v ref + 0.05 v tt v others 2.0 v v il b port 0.0 v ref ? 0.05 v others 0.8 v v ref gtlp 0.74 1.0 1.1 v v ik v cc = 3.0v i i = ? 18 ma ? 1.2 v v oh a port v cc = min to max (note 9) i oh = ? 100 av cc ? 0.2 v cc = 3.0v i oh = ? 12 ma 2.4 v i oh = ? 24 ma 2.2 v ol a port v cc = min to max (note 9) i ol = 100 a0.20 v v cc = 3.0v i ol = 12 ma 0.40 i ol = 24 ma 0.50 b port v cc = 3.0v i ol = 40 ma 0.20 v i ol = 80 ma 0.40 i ol = 100 ma 0.50 i i a port v cc = 3.6v v i = v cc or 0v 10 a control pins v cc = 3.6v v i = v cc or 0v 10 a b port v cc = 3.6v v i = v tt or gnd 10 a i off except v cc = 0v i or v o = 0 to 100 a v erc v cc i i(hold) a port v cc = 3.0v v i = 0.8v 75 a v i = 2.0v ? 75 v cc = 3.6v v i = 0 to v cc 500
5 www.fairchildsemi.com gtlp16t1655 dc electrical characteristics (continued) note 8: all typical values are at v cc = 3.3v, and t a = 25 c. note 9: for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. note 10: this is specified by characterization but not tested. note 11: this is the increase in supply current for each input that is at the specified ttl voltage level rather than v cc or gnd. live insertion characteristics over recommended operating free-air temperature range, v ref = 1.0v (unless otherwise noted). ac operating requirements (gtlp) over recommended ranges of supply voltage and operating free-air temperature, v tt = 1.5v and v ref = 1.0v (unless otherwise noted). symbol test conditions min typ max units (note 8) i ozh a port v cc = 3.6v v o = v cc 10 a b port v o = 1.5v 10 i ozl a port v cc = 3.6v v o = 0v ? 10 a b port v o = 0.4v ? 10 i ozpu a port v cc = 0 to 1.5v v o = 0.5 to 3v 50 a (note 10) oe = 0 or v cc i ozpd a port v cc = 1.5 to 0v v o = 0.5 to 3v 50 a (note 10) oe = 0 or v cc i cc a or b ports v cc = 3.6 outputs high 55 ma (v cc )i o = 0 outputs low 55 v i = v cc or gnd outputs disabled 55 ? i cc a port and v cc = 3.6v one input at 0 1 ma (note 11) control pins a or control v cc ? 0.6 inputs at v cc or gnd c i control pins v i = v cc or 0 5.8 7.0 a port v i = v cc or 0 8.0 9.5 pf b port v i = v cc or 0 8.3 9.9 parameter test conditions min typ max units i cc b port v cc = 0 to 3v v o = 0 to 1.2v 5 ma (v cc bias) v cc = 3.0 to 3.6v v i (v cc bias) = 3 to 3.6v 10 a v o b port v cc = 0v i (v cc bias) = 3.3v 1.1 v i o b port v cc = 0v i (v cc bias) = 3 to 3.6v v o = 0.4 ? 1 a v cc = 0 to 3.6v oe = 3.3v 100 v cc = 0 to 1.5v oe = 0 to 3.3v 100 parameter min max unit f max maximum clock frequency 160 mhz t width pulse duration le high 3.0 ns clk high or low 3.0 t su setup time data before clk 2.5 ns data before le (clk = x) 2.5 t hold hold time data after clk 0.5 ns data after le (clk = x) 0.5
www.fairchildsemi.com 6 gtlp16t1655 b to a ac electrical characteristics (gtlp) over recommended range of supply voltage and operating free-air temperature, v ref = 1.0v, v tt = 1.5v, v erc = v cc or gnd (unless otherwise noted). c l = 30 pf for b port and c l = 50 pf for a port. note 12: all typical values are at v cc = 3.3v, and t a = 25 c. parameter from to min typ max unit (input) (output) (note 12) f max 160 mhz t plh ba1.04.7 ns t phl 1.5 4.8 t plh leab a 1.2 4.0 ns t phl 1.2 3.8 t plh clk a 1.2 4.0 ns t phl 1.2 4.0 t plz/hz oe a1.44.5 ns t pzh/zl 1.0 4.0 t plz/hz oeba a1.24.9 ns t pzh/zl 1.0 4.0
7 www.fairchildsemi.com gtlp16t1655 a to b ac electrical characteristics (gtlp) over recommended range of supply voltage and operating free air temperature, v = 1.0v, v tt = 1.5v (unless otherwise noted). c l = 30 pf for b port and c l = 50 pf for a port. note 13: all typical values are at v cc = 3.3v and t a = 25 c symbol from to min type max units (input) (output) (note 13) f max 160 mhz t plh ab2.6 5.7 ns t phl v erc = v cc 0.8 4.5 t plh ab2.0 4.9 ns t phl v erc = gnd 0.7 4.0 t plh leab b 2.6 5.7 ns t phl v erc = v cc 0.8 4.0 t plh leab b 2.2 4.9 ns t phl v erc = gnd 0.7 4.0 t plh clk b 2.8 5.7 ns t phl v erc = v cc 1.0 4.0 t plh clk b 2.3 5.0 ns t phl v erc = gnd 0.8 4.0 t plh oe b2.7 5.8 ns t phl v erc = v cc 0.6 4.0 t plh oe b2.1 4.9 ns t phl v erc = gnd 1.0 4.0 t plh oeab b2.6 5.8 ns t phl v erc = v cc 0.6 4.0 t plh oeab b2.0 4.9 ns t phl v erc = gnd 0.6 3.5 t fall/rise transition time, b outputs (0.6v to 1.3v) 0.7/0.7 2.0/2.5 ns v erc = v cc t fall/rise transition time, b outputs (0.6v to 1.3v) 0.7/0.7 1.5/2.0 ns v erc = gnd
www.fairchildsemi.com 8 gtlp16t1655 extended electrical characteristics (gtlp) over recommended ranges of supply voltage and operating free-air temperature v ref = 1.0v (unless otherwise noted). c l = 30 pf for b port and c l = 50 pf for a port. note 14: all typical values are at v cc = 3.3v, and t a = 25 c. note 15: t oshl /t oslh and t ost ? output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. the specifications are given for specific worst case v cc and temperature and apply to any outputs switching in the same direction either high-to-low (t oshl ) or low-to-high (t oslh ) or in opposite directions both hl and lh (t ost) . this parameter is guaranteed by design and statistical process distribution. actual skew values between the gtlp outputs could vary on the backplane due to the loading an d impedance seen by the device. note 16: t pv ? part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device. the parameter is specified for a specific worst case v cc and temperature. this parameter is guaranteed by design and statistical process distribution. actual skew values between the gtlp outputs could vary on the backplane due to the loading and impedance seen by the device. note 17: due to the open drain structure on gtlp outputs, t ost and t pv(lh) in the a-to-b direction are not specified. skew on these paths is dependent on the v tt and r t values on the backplane. symbol from to min typ max unit (input) (output) (note 14) t oslh (note 15) a b 0.4 1.0 ns t oshl (note 15) 0.4 1.0 ns t pv(hl) (note 16) (note 17) a b 1.5 ns t oslh (note 15) clkab b 0.3 0.9 ns t oshl (note 15) 0.3 0.6 ns t pv(hl) (note 16)(note 17) clkab b 1.2 ns t oslh (note 15) b a 0.3 1.0 ns t oshl (note 15) 0.3 1.0 ns t ost (note 15) b a 0.6 1.5 ns t pv (note 16) b a 1.6 ns t oslh (note 15) clkab a 0.3 0.6 ns t oshl (note 15) 0.3 0.6 ns t ost (note 15) clkab a 0.5 1.0 ns t pv (note 16) clkab a 1.1 ns
9 www.fairchildsemi.com gtlp16t1655 ac operating requirements (gtl) over recommended ranges of supply voltage and operating free-air temperature, v tt = 1.2v and v ref = 0.8v (unless otherwise noted). b to a ac electrical characteristics (gtl) over recommended range of supply voltage and operating free air temperature, v ref = 0.8v, v tt = 1.2v, v erc = v cc or gnd (unless otherwise noted). c l = 30pf for b port and c l = 50 pf for a port. note 18: all typical values are at v cc = 3.3v and t a = 25 c. parameter min max units f max maximum clock frequency 160 mhz t width pulse duration le high 3.0 ns clk high or low 3.0 ns t su setup time data before clk 2.5 ns data before le (clk = x) 2.5 t hold hold time data after clk 0.5 ns data after le (clk = x) 0.5 parameter from to min typ max units (input) (output) (note 18) f max 160 mhz t plh b a 1.0 4.7 ns t phl 1.2 4.8 t plh leba a 1.0 4.4 ns t phl 1.1 4.0 t plh clk a 1.0 4.2 ns t phl 1.1 4.1 t plz/hz oe a1.5 4.6ns t pzh/zl 1.2 4.2 t plz/hz oeba a1.2 4.9ns t pzh/zl 1.0 4.0
www.fairchildsemi.com 10 gtlp16t1655 a to b ac electrical characteristics (gtl) over recommended range of supply voltage and operating free air temperature, v ref = 0.8v, v tt = 1.2v (unless otherwise noted). c l = 30 pf for b port and c l = 50 pf for a port. note 19: all typical values are at v cc = 3.3v and t a = 25 c. symbol from to min typ max units (input) (output) (note 19) f max 160 mhz t plh ab2.25.7 ns t phl v erc = v cc 1.0 4.7 t plh ab1.54.8 ns t phl v erc = gnd 0.9 4.0 t plh leab b 2.2 5.7 ns t phl v erc = v cc 1.0 4.1 t plh leab b 1.7 5.0 ns t phl v erc = gnd 0.9 4.4 t plh clk b 2.8 5.8 ns t phl v erc = v cc 1.0 4.3 t plh clk b 2.3 5.0 ns t phl v erc = gnd 1.0 4.3 t plh oe b2.5 5.8 ns t phl v erc = v cc 0.8 4.3 t plh oe b1.7 4.9 ns t phl v erc = gnd 0.9 4.3 t plh oeab b2.2 5.8 ns t phl v erc = v cc 0.8 4.3 t plh oeab b1.7 4.9 ns t phl v erc = gnd 0.9 3.8 t fall/rise transition time, b outputs (0.6v to 1.3v) 0.7/0.7 2.0/2.5 ns v erc = v cc t fall/rise transition time, b outputs (0.6v to 1.3v) 0.7/0.7 1.5/2.0 ns v erc = v cc
11 www.fairchildsemi.com gtlp16t1655 extended electrical characteristics (gtl) over recommended ranges of supply voltage and operating free-air temperature v ref = 0.8v (unless otherwise noted). c l = 30 pf for b port and c l = 50 pf for a port. note 20: all typical values are at v cc = 3.3v, and t a = 25 c. note 21: t oshl /t oslh and t ost ? output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. the specifications are given for specific worst case v cc and temperature and apply to any outputs switching in the same direction either high-to-low (t oshl ) or low-to-high (t oslh ) or in opposite directions both hl and lh (t ost) . this parameter is guaranteed by design and statistical process distribution. actual skew values between the gtl outputs could vary on the backplane due to the loading and impedance seen by the device. note 22: t pv ? part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device. the parameter is specified for a specific worst case v cc and temperature. this parameter is guaranteed by design and statistical process distribution. actual skew values between the gtl outputs could vary on the backplane due to the loading and impedance seen by the device. note 23: due to the open drain structure on gtl outputs, t ost and t pv(lh) in the a-to-b direction are not specified. skew on these paths is dependent on the v tt and r t values on the backplane. symbol from to min typ max unit (input) (output) (note 20) t oslh (note 21) a b 0.4 1.0 ns t oshl (note 21) 0.4 1.0 ns t pv(hl) (note 22) (note 23) a b 1.5 ns t oslh (note 21) clkab b 0.3 0.9 ns t oshl (note 21) 0.3 0.6 ns t pv(hl) (note 22)(note 23) clkab b 1.2 ns t oslh (note 21) b a 0.3 1.0 ns t oshl (note 21) 0.3 1.0 ns t ost (note 21) b a 0.6 1.5 ns t pv (note 22) b a 1.6 ns t oslh (note 21) clkab a 0.3 0.6 ns t oshl (note 21) 0.3 0.6 ns t ost (note 21) clkab a 0.5 1.0 ns t pv (note 22) clkab a 1.1 ns
www.fairchildsemi.com 12 gtlp16t1655 test circuits and timing waveforms test circuit for a outputs test circuit for b outputs note a: c l includes probes and jig capacitance. note b: for b port, c l = 30 pf is used fort worst case. voltage waveform - propagation delay times voltage waveform - setup and hold times voltage waveform - pulse width voltage waveform - enable and disable times output waveform 1 is for an output with internal conditions such that the output is low except when disabled by the control output output waveform 2 is for an output with internal conditions such that the output is high except when disabled by the control output input and measure conditions all input pulses have the following characteristics: frequency = 10mhz, t rise = t fall = 2 ns, z o = 50 ? the outputs are measured one at a time with one transition per measurement test s t plh /t phl open t plz /t pzl 6v t phz /t pzh gnd a or lvttl pins b or gtlp pins v inhigh 3.0 1.5 v inlow 0.0 0.0 v m 1.5 1.0 v x v ol + 0.3v n/a v y v oh ? 0.3v n/a
13 www.fairchildsemi.com gtlp16t1655 16-bit lvttl/gtlp universal bus transceiver with high drive gtlp and individual byte controls physical dimensions inches (millimeters) unless otherwise noted 64-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd64 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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